1. Field of the Invention
This invention relates to semiconductor circuits and particularly to input circuits for semiconductor integrated circuit devices operating in a synchronous mode.
2. Description of the Prior Art
In processor designs where there is provided a local or on chip cache, addresses are available sequentially from a fixed point unit. The addresses are provided in time to make the cycle boundry. Early addresses occur significantly before the next cycle. These early addresses are complementary dual-rail signals and are used in slower macros in the cache. The late addresses are single ended and are clocked in with the system clock. These slow addresses go to the faster macros.
Cache architecture as well as address input buffers and True/Complement (T/C) generators can be implemented to take advantage of these early addresses. Because of the presence of Automatic Built In Self Test (ABIST) and other possible inputs such as those from a Data Unit Controller the Address T/C generators are required to accept a variety of input wave forms. For example addresses from the Data Unit might be static/DC or self resetting pulsed inputs while the inputs from other circuits could be dynamic self resetting or clock resetting when provided by a fixed point unit.